The present invention relates generally to processing systems and, more particularly, to a crossbar for use in a processing system, wherein the crossbar is configurable for transferring bit width between crossbar usage paths.
A crossbar is a chip or chip component commonly used to provide high-frequency links among a plurality of sources and destinations in a VLSI (very large scaled integration) based processing system. When used in a multiprocessor system, a crossbar typically provides a fixed amount of bandwidth at each crossbar port, allowing only a certain number of bits per second to be transferred from a source to a destination. In a multiprocessor system, however, utilization levels for processors typically vary according to the particular jobs, i.e. programs, the processors are assigned to execute. Additionally, other network agents such as input/output (I/O) controllers, memory controllers and cache memory, located, for example, on separate VLSI chips, are commonly connected to one another through crossbars. Performance of heavily utilized processors and bandwidth-intensive system agents, e.g. cache memory controllers delivering data to many processors, could be improved if crossbar connections were to provide higher bandwidths than those currently available.
Thus a need exists for a crossbar that can be configured to provide relatively less bandwidth for relatively less bandwidth-intensive system agents, and to provide relatively more bandwidth for agents needing more bandwidth for optimal performance. It can be expensive, however, in terms of engineering effort and schedule to develop a VLSI chip, particularly a high-frequency custom design. Thus it would be desirable to design flexibility into existing VLSI chips so that they can be put to use in a variety of applications.
In one preferred form, the invention is directed to a crossbar for providing connections among a plurality of system agents such as processors, memories and controllers. The crossbar includes a plurality of control sub-ports and a plurality of mini-ports selectively configurable as a plurality of connection points for providing the connections. Each control sub-port includes a domain of mini-ports that the control sub-port is configured to selectively control. Each mini-port is configurable to select one from a plurality of the control sub-ports having domains that include the selecting mini-port. Each of the connection points includes a corresponding one of the control sub-ports and each mini-port selecting the corresponding control sub-port.
The above crossbar can be configured to provide amounts of bandwidth specifically tailored to the performance needs of various system agents to be connected across the crossbar. Thus bottlenecks across the crossbar can be eliminated or reduced, and overall performance of the processing system can be enhanced.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.